Laboratory 2 · CEG 3155 · uOttawa · Fall 2026

Fixed-point arithmetic

What the laboratory asks for, what the hardware does, and the order to do the work in. Ten minutes of reading.

Lab 2 handout Lecture 6, floating point adder Lecture 7, signed numbers and overflow Lecture 8, multiplication and division

Pre-lab

Due before you arrive

A four-bit signed adder and subtractor, built, simulated and brought with you.

Four bits, signed, two's complement. Range −8 to +7. Subtraction is addition of the two's complement, which the circuit forms by inverting every bit of y and setting the carry in to 1, both from the same Add / Sub line.
Overflow. The unit has to report it. In two's complement it is the carry into the sign bit against the carry out of it, so OverflowOut = c₄ ⊕ c₃, and it cannot be read off the carry out alone.
Code it in RTL and structural VHDL. Section 3.2 walks the design, section 8 holds the coding rules.
Simulate it, showing several pairs added and several subtracted, each giving the right answer, and at least one pair that overflows.
Present and explain it to the teaching assistant at the start of the session. Expect questions.
Keep the signed sheet. It is handed in with the final report.

Figure 6 of the handout at four bits. Add / Sub low adds, high subtracts: it inverts every bit of y through the exclusive OR gates and supplies the carry in, which together make the two's complement of y.

Lab

The marks live here

Two ASM designs, then an ALU built around them.

The five stages of Laboratory 1, run twice, once for the signed multiplier and once for the signed divider. Each gets its own pseudocode, chart, datapath, detailed chart and control logic.

Write the algorithm as pseudocode. Nothing is supplied this time. Laboratory 1 handed you the pseudocode and asked you to close its gaps. Here you write it from the problem, for each of the two units.
Turn the pseudocode into an ASM chart. Rectangles for states, one clock step each, diamonds for tests. Every register the design needs is decided here.
Draw the datapath. Registers, the paths between them, a device wherever a value is transformed on the way, and a selector wherever a register is fed from more than one place. This stage produces the control signal names.
Redraw it as the detailed ASM chart, with every movement of data replaced by the control signals that cause it.
Design the control logic by the one flip flop per state method.

Then the ALU around them, which is where the points that are easy to miss live.

All four operations behind one output. OperationSelect[1..0] chooses what reaches MuxOut[7..0], in the pairing Table 4 of the handout gives.
Three status outputs. CarryOut, ZeroOut and OverflowOut, all three brought out of the ALU.
The seven-segment display. All eight digits on the board share one set of cathodes, so a display controller clocked from CLK100MHZ multiplexes them in time, driving seg[6..0] and an[7..0].
Four-bit arithmetic, wider registers. Every operation is four bits so the result fits the display, but some registers have to be eight, the product register being the obvious one.
Signed all the way through. You may not flip a negative operand positive, multiply or divide, and repair the sign afterwards. The handout closes that route in bold.

A report that shows a working display and skips the charts loses most of the marks.

1. The gist

A four-bit arithmetic logic unit for signed numbers. It takes two four-bit operands and a two-bit operation select, performs one of four operations on them, and shows the result on the board's seven-segment display.

Four operations, chosen by two switches
OperationSelect	Result on MuxOut[7..0]	Where it comes from
00	four-bit sum	the pre-lab adder
01	four-bit difference	the pre-lab subtractor
10	eight-bit product	the multiplier you design
11	four-bit quotient and remainder	the divider you design

Three status lights come out alongside the result: CarryOut for a carry or borrow, ZeroOut when the result is zero, and OverflowOut when the operation overflowed.

The operands are signed, and the handout closes the easy route explicitly. You may not detect a negative operand, flip it positive, multiply or divide, and fix the sign afterwards. The multiplier and the divider have to handle signed values directly. That single sentence is what makes this laboratory harder than it looks.

Lecture 6 is the one worked example in the course of all five ASM stages on a single problem. Its subject is a floating point adder, which is not the arithmetic of this laboratory, so take the method from it and not the mathematics: how the pseudocode became a chart, how the chart produced a datapath, and how the detailed chart produced the control logic. Laboratory 2 asks for that sequence twice over.

Lecture 8 is the closest to the work itself, carrying multiplication, division and signed multiplication and division, along with the carry lookahead adder that the bonus asks for. Lecture 7 covers signed and unsigned numbers, addition and subtraction, and arithmetic overflow, which is the pre-lab and the OverflowOut status signal.

2. The kit

What the laboratory runs on
Board	Digilent Nexys A7-100T, Xilinx Artix-7
Software	Xilinx Vivado, Windows or Linux x86 only
Arithmetic	four bits, so the result fits the seven-segment display
Team	two people
Due	Wednesday 14 October, midnight, Brightspace

GClock is a push button. Laboratory 1 divided the 100 MHz clock down to about one step per second, and here you supply each edge yourself. Here you step the circuit by hand, and the Nexys A7 buttons are active high and not debounced, so one press can register as several edges. The multiplier and the divider each need a fixed number of steps before the answer is valid, so press deliberately and count.

CLK100MHZ is still there, and it drives the display only. The seven-segment digits share one set of cathodes, so a supplied display controller refreshes them in turn from the oscillator. It is not the clock your arithmetic runs on.

3. What is happening inside

Four arithmetic units, one output multiplexer and a display controller.

The adder and subtractor are the pre-lab, built around a ripple carry adder. Subtraction is addition of the two's complement.
The multiplier is sequential. It works through the operand a bit at a time over several clock steps, which is why the product register is eight bits wide while the operands are four.
The divider is sequential too, and produces a four-bit quotient and a four-bit remainder, both packed into the eight-bit output.
The output multiplexer selects one of the four results onto MuxOut[7..0], padding the four-bit answers with zeros.

Because the multiplier and divider take several steps, each needs a Done state, and the result is only valid once it is reached. That is a difference from Laboratory 1, where every step produced a finished answer.

4. What the reset does

GReset forces every flip flop in the design to a known value, so the circuit starts from a defined state. The fabric powers up in an arbitrary one. It reaches every functional block, and section 8 requires that.

Like GClock it is a push button on the board, so the demonstration starts by pressing reset and then stepping.

5. The rules that cost marks

VHDL only. Verilog is refused.
Structural modelling. Behavioural is refused, with one stated exception: the supplied display controller, which is board glue for the multiplexed display.
RTL design and coding is mandatory.
The top level is a structural VHDL entity. Vivado uses an HDL flow, where the older tool used graphical entry, so this replaces what Laboratory 1 asked for.
Build every block yourself. No Xilinx IP, no LPM cores, nothing from the internet. Atomic modules down to the D flip flop, the one-bit adder and the one-bit comparator are written in VHDL.
Synchronous and globally resettable, with clock and reset in every functional block.
Signed operands handled directly. Converting negatives to positives and correcting afterwards is named and refused.
Simulate all four operations and check the results against hand calculations.
Demonstrate a working version to the TA before the report is due.

Five bonus marks are on offer. Replace the ripple carry adder with a four-bit carry lookahead adder. The handout asks for the modifications discussed, with no need to redraw every component, and the new design demonstrated to the teaching assistant. Section 5.4.1 of the textbook covers the design.

6. How to approach it

The pre-lab comes first and it is a gate. It has to exist, simulate correctly and be explained before the session begins, so it is the first thing to build, whatever order the report ends up in.

Then the two algorithms, on paper, before any VHDL. Signed multiplication and signed division are where the thinking is, and the ban on converting to positive first is the constraint that shapes both. Work them as pseudocode until you can run them by hand on a negative operand.

Then the ASM stages for each unit, in order. Chart, datapath, detailed chart, control logic. Each reads its input off the one before it, so a wrong chart costs everything after it.

Then the VHDL, from the bottom up, testing each block on its own before wiring it into the next. The adder from the pre-lab is already done and tested, which is a working foundation for the other three.

Integration last, then the output multiplexer, then the board.

7. What goes in the report

The structure is fixed by the report guidelines: cover page, objectives, problem and solution discussion, verification, lab discussion, conclusion and appendices. The marking scheme puts the weight on the algorithmic solution, the components, the simulation and the demonstration.

Timing simulations with explanation, for every VHDL source file
All source files described and commented
A flowchart and a block diagram of the solution
The ASM charts, datapaths and control logic for both the multiplier and the divider
Your solution described in your own words, without pronouns and in the passive voice
The design obstacles and how they were overcome
All source code appended, and the files submitted alongside

Twenty five pages maximum, including cover page, contents and appendices, losing a mark for every page over. With two full ASM designs to present, this binds on Laboratory 2 in a way it did not on Laboratory 1.