Laboratory 3

The behaviour above is the easy part. The marks are for following a fixed design method, called ASM, and showing your working at every stage. Five stages, in this order, and each one reads its input off the one before it.

1. Write the algorithm as pseudocode. Plain register transfers, one line each, with the branches written as if and else. No hardware named yet. Laboratory 1 was given a draft in its handout, so expect the same here.
2. Turn the pseudocode into an ASM chart. A flowchart with two shapes: a rectangle for a state, which takes exactly one clock step, and a diamond for a test, which takes no time at all. Every register the design needs is decided here.
3. Draw the datapath. Read the hardware off the chart. Every register named in the chart becomes real storage, every value moved becomes a wire, anything transformed on the way gets a device in the path, and a register fed from more than one place gets a selector. This stage produces the list of control signal names.
4. Redraw it as the detailed ASM chart. The same chart again, with every movement of data replaced by the names of the control signals that cause it.
5. Design the control logic. Build the state machine that produces those signals, using the one flip flop per state method, which gives every state in your chart its own flip flop.

Only after all five do you write any VHDL. Simulating the result and running it on the board come after that, and neither is one of the five stages: they are how you check that stage 5 agrees with stage 1.

A report that shows working LEDs and skips the charts loses most of the marks.